A typical clock recovery circuit includes a phase detector, such as that shown in FIG. 1A. The phase detector of FIG. 1A is of the type known in the art as an Alexander phase detector, or a Bang-Bang phase detector. A received data signal on line 102 is sampled by the flip-flop 106 on the rising edge of the clock signal on line 104. The data signal is again sampled on the falling edge of the clock by the flip-flop 108. On the next rising edge of the clock signal, the data signal is again sampled by flip-flop 106, while the previous samples are shifted into flip-flops 110 and 112. Thus, the data samples held in flip-flops 110, 112, 106 correspond to samples A, B, and C, respectively, as shown in FIG. 1B. If the outputs of flip-flop 106 and 110 are both the same (A=C), then the outputs of exclusive OR (XOR) gates 116, 120, are both equal to zero and no phase update occurs. On the other hand, the presence of either a falling edge (from high to low) or a rising edge (from low to high) in the data signal will result in different values for A and C (A≠C), which will validate the phase update signals.
If A and C are not the same, then the outputs depend on the value of B. If A=B, indicating that the clock is early (the falling edge of the clock occurs during the same bit time as sample A), the output 116 of XOR gate 114 is low and the output 120 of XOR gate 118 is high. And if B=C indicating that the clock is late (the falling edge of the clock occurs during the same bit time as sample C), then the logic outputs at 116 and 120 are reversed. Thus, the XOR gates 114, 118 provide the phase adjustment signals.
In optical communication systems, optical fiber transmission may induce nonlinear distortion of the signal waveform. As a result, the location of the bit transitions relative to the mid-bit position tends to vary depending on the data sequence transmitted. In addition, certain pulse sequences result in a rising edge followed by a falling edge where the edges are less than one symbol period apart. Therefore, the phase detector of FIG. 1A, and variants thereof, may have difficulty recovering an accurate clock signal due to the jitter induced by the variance in the pulse shapes. Consequently, an improvement is desired.